Itanium 2 processor, microprocessors, high-end enterprise, business intelligence, databases, enterprise resource planning, SCM, computing, computer-aided engineering
In early 2003, Intel, the largest producer of microprocessors in the world, launched the company's new 64-bit microprocessor, the Itanium 2. Intel spent billions of dollars on Itanium 2 to take on IBM and Sun Microsystems [Sun] in the $25 bn market for the 64-bit servers.
The processor also boasts advanced reliability features, including extensive error detection and correction on the processor's major data structures. Itanium 2 also has an advanced Machine Check Architecture for intelligent error management and recovery of complex platform errors to prevent data loss, corruption and down time.
The Itanium 2 is also socket-compatible with two future generations of Itanium family processors to allow them to be easily swapped into existing Itanium 2-based systems. This extended the value and longevity of customer investments in Itanium 2-based platforms. In addition, Intel has five future Itanium processor family products in development, with designs already underway that reached into the second half of the decade. But Intel faced major challenges in gaining acceptance for 64-bit chips. The shift to 64-bit computing is not merely a matter of upgrading the Pentium. Itanium 2 requires computer makers to redesign their hardware and software companies, effectively requiring them to rewrite all their code. While Itanium I has been a failure, the timing of the launch of Itanium 2 is a cause for concern. Following the dotcom crash, the tech market is witnessing a major downturn.
1] EPIC technology breaks through the sequential nature of conventional processor architectures by allowing the software to communicate explicitly to the processor when operations can be done in parallel. Reducing the number of branches and branch mispredicts, and reducing the effects of memory-to-processor latency has increased performance. EPIC technology also reduces hardware complexity. EPIC was jointly designed by Intel and HP and introduced in 1997.
2] Three levels of cache reduce memory latency; Level 1 cache, Level 2 cache and Level 3 cache. 3 MB Level 3 cache is a pool of memory integrated into the processor for performance level of 3 MB.
More ICMR India Case Studies
|Business Environment||Business Ethics||Business Reports||Business Strategy|
|Corporate Governance||Economics||Enterprise Risk Management||Finance|
|HRM||Innovation||Insurance||IT and Systems|
|Leadership and Entrepreneurship||Marketing||Miscellaneous||Operations|
|Project Management||Short Case Studies||Cases in other Languages||Free Case Studies|